Espressif Systems /ESP32-C6 /SPI0 /SPI_MEM_TIMING_CALI

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Interpret as SPI_MEM_TIMING_CALI

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_TIMING_CLK_ENA)SPI_MEM_TIMING_CLK_ENA 0 (SPI_MEM_TIMING_CALI)SPI_MEM_TIMING_CALI 0SPI_MEM_EXTRA_DUMMY_CYCLELEN 0 (SPI_MEM_DLL_TIMING_CALI)SPI_MEM_DLL_TIMING_CALI 0 (UPDATE)UPDATE

Description

SPI0 flash timing calibration register

Fields

SPI_MEM_TIMING_CLK_ENA

The bit is used to enable timing adjust clock for all reading operations.

SPI_MEM_TIMING_CALI

The bit is used to enable timing auto-calibration for all reading operations.

SPI_MEM_EXTRA_DUMMY_CYCLELEN

add extra dummy spi clock cycle length for spi clock calibration.

SPI_MEM_DLL_TIMING_CALI

Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.

UPDATE

Set this bit to update delay mode, delay num and extra dummy in MSPI.

Links

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